Application of a Silicon Compiler to VLSI (Very Large Scale Integrated Circuits) Design of Digital Pipelined Multipliers
A 1984 technical report from the Naval Postgraduate School in Monterey, California, compiled by D J Carlson for the Defense Technical Information Center, documenting a silicon compiler used to lay out pipelined digital multipliers as VLSI chips. The pictures are engineering diagrams: a block plan of data path and control with pad rings, a stacked multiplier cell schematic with clock lines, chip layout plots, and a two-phase clocked storage circuit with timing waveforms, all in plain black linework a designer could borrow for schematic or technical diagram styling.
