An Integrated Circuit Fault Model for Digital Systems
A 1976 technical report by Mark Loren Ketelsen of the Coordinated Science Laboratory at the University of Illinois, prepared for the defense research community, on fault modelling in integrated circuits and digital systems. Its pictures are plain line diagrams: circles joined by solid and dashed lines forming cube-like state graphs, transition arrows between labelled state nodes, and a small logic tree with AND and OR gates, numbered connections and an input variable; a designer might borrow the clean node-and-arrow diagram style for flowcharts or network graphics.
